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PF805-04
SRM20V100LLMX7 SRM20V100LLMX7
1M-Bit Static RAM
ge lta Vo ion wt Lo pera cts O odu Pr
s DESCRIPTION
q Low Supply Voltage q Wide Temperature Range q Low Supply Current q Access Time 70ns (2.7V) q 131,072 Wordsx8-Bit Asynchronous
The SRM20V100LLMX7 is an 131,072 wordsx8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. And --25 to 85C operating temperature range makes it ideal for portable equipment. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.
s FEATURES
q Wide temperature range ..... -25 to 85C q Fast Access time ................. SRM20V100LLMX7 70ns (Max.) q Low supply current .............. standby: 0.6A (Typ.): LL Version 0.3A (Typ.): SL Version operation: 8mA/1MHz (Typ.) q Completely static ................. No clock required q Supply voltage..................... 2.7V to 3.6V q TTL compatible inputs and outputs q 3-state output with wired-OR capability q Non-volatile storage with back-up batteries SOP6-32pin (plastic) q Package ...... SRM20V100LLMX7 SRM20V100LLTX7 TSOP ( I )-32pin (plastic) SRM20V100LLRX7 TSOP ( I )-32pin-R1 (plastic) SRM20V100LLKX7 Slim-TSOP ( I )-32pin (plastic) SRM20V100LLYX7 Slim-TSOP ( I )-32pin-R1 (plastic)
s PIN CONFIGURATION
(SOP6)
N.C. A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/01 I/02 I/03 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/08 I/07 I/06 I/05 I/04
SRM20V100LLMT
(TSOP/Slim-TSOP)
A11 A9 A8 A13 WE CS2 A15 VDD N.C. A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/08 I/07 I/06 I/05 I/04 VSS I/03 I/02 I/01 A0 A1 A2 A3
SRM20V100LLTX/KX
s BLOCK DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CS1 CS2
10
X Decoder
(TSOP-R1/Slim-TSOP-R1)
1024 Memory Cell Array 1024x128x8
128x8
7
128
Column Gate
A4 A5 A6 A7 A12 A14 A16 N.C. VDD A15 CS2 WE A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SRM20V100LLRX/YX
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 I/01 I/02 I/03 VSS I/04 I/05 I/06 I/07 I/08 CS1 A10 OE
Address Buffer
Y Decoder
CS1, CS2 Chip Control
8
PIN DESCRIPTION
A0 to A16 Address Input WE Write Enable OE Output Enable CS1, CS2 Chip Select I/O1 to I/O8 Data I/O VDD Power Supply (2.7V to 3.6V) VSS Power Supply (0V) N. C. No connection
OE WE
OE, WE Chip Control
I/O Buffer
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
1
s ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input voltage Input/Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time
TVI,
(VSS = 0V) Ratings -0.5 to 4.6 -0.5 to VDD+0.3 -0.5 to VDD+0.3 0.5 -25 to 85 -65 to 150 260C, 10s (at lead)
Symbol VDD VI VI/O PD Topr Tstg Tsol
Unit
V V V W C C --
VI/O (Min.) = -3.0V (Pulse width is 50ns)
s DC RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Input voltage
TIf
Symbol VDD VSS VIH VIL
Conditions -- -- -- --
Min. 2.7 0 2.2 -0.3T
(VSS = 0V, Ta = -25 to 85C) Typ. Max. Unit V 3.0 3.6 V 0 0 V -- VDD+0.3 0.4 V --
pulse width is less than 50ns, it is -3.0V
s ELECTRICAL CHARACTERISTICS q DC Electrical Characteristics
Parameter Input leakage Output leakage Symbol ILI ILO IDDS Standby supply current IDDS1 IDDA Average operating current IDDA1 Operating supply current High level output voltage Low level output voltage IDDO VOH VOL Conditions VI=0 to VDD CS1 = VIH or CS2 = VIL or WE = VIL or OE = VIH, VIO = 0 to VDD CS1 = VIH or CS2 = VIL CS1 = CS2VDD--0.2V or CS20.2V VI = VIL, VIH II/O = 0mA, tcyc = Min. VI = VIL, VIH II/O = 0mA, tcyc = 1s VI = VIL, VIH II/O = 0mA VDD3V, IOH = -2.0mA IOH = -100A VDD3V, IOL = -2.0mA IOL = 100A
DD=3.0V
(VDD = 2.7 to 3.6V, VSS = 0V, Ta = -25 to 85C) Min. -1 -1 -- LL SL -- -- -- -- -- 2.4 VDD--0.2 -- -- Typ.T -- -- -- 0.6 0.3 20 8 8 -- -- -- -- Max. 1 1 1.0 60 30 35 15 15 -- -- 0.4 0.2
Unit
A A mA A mA mA mA V V
TTypical values are measured at Ta=25C and V
q Terminal Capacitance
Parameter Address Capacitance Input Capacitance I/O Capacitance Symbol CADD CI CI/O Conditions VADD=0V VI=0V VI/O=0V Min. -- -- -- Typ. -- -- --
(f = 1MHz, Ta = 25C) Max. 8 8 10
Unit
pF pF pF
2
SRM20V100LLMX7
q AC Electrical Characteristics r Read Cycle
Parameter Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Chip select1 output set time Chip select1 output floating Chip select2 output set time Chip select2 output floating Output enable output set time Output enable output floating Output hold time Symbol tRC tACC tACS1 tACS2 tOE tCLZ1 tCHZ1 tCLZ2 tCHZ2 tOLZ tOHZ tOH Conditions
(VDD = 2.7V to 3.6V, VSS = 0V, Ta = -25 to 85C) Min. 70 -- -- -- -- 5 -- 5 -- 0 -- 10 Max. -- 70 70 70 40 -- 30 -- 30 -- 30 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
T1
T2
T1
r Write Cycle
Parameter Write cycle time Chip select time1 Chip select time2 Address enable time Address setup time Write pulse width Address hold time Input data setup time Input data hold time WE Output floating WE Output setup time
T
(VDD = 2.7V to 3.6V, VSS = 0V, Ta = -25 to 85C) Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW Conditions Min. 70 60 60 60 0 55 0 30 0 -- 5
T
T1
T2
Max. -- -- -- -- -- -- -- -- -- 30 --
Unit ns ns ns ns ns ns ns ns ns ns ns
+3V
1 Test Conditions 1. Input pulse level: 0.4V to 2.4V 2. tr = tf = 5ns 3. Input and output timing reference levels : 1.5V 4. Output load CL = 100pF
I/O CL
+3V
2 Test Conditions 1. Input pulse level : 0.4V to 2.4V 2. tr = tf = 5ns 3. Input timing reference levels: 1.5V 4. Output timing reference levels:
I/O CL
1.0k
1.0k
920
200mV (the level displaced from stable output voltage level) 5. Output load CL = 5pF
920
CL=100pF (Includes Jig Capacitance)
CL=5pF (Includes Jig Capacitance)
3
q Timing chart
rRead CylcleT1
Address tACC tACS1 CS1 tCLZ1 tACS2 CS2 tCLZ2 tOE tOLZ Dout tOHZ tCHZ1 tCHZ2 WE tCLZ1 Dout tDW Din tDH tOH Address CS1 CS2 tWR tWHZ tAS tAW tCW1 tWR tRC
rWrite Cycle (1) (CS1 Control)T2
tWC
OE
rWrite Cycle (2) (CS2 Control)T2
tWC Address tAW tCW2 CS1 tAS CS2 WE tWHZ Dout tCLZ2 Din tDW tDH tWP tWR
rWrite Cycle (3) (WE Control)T3, T4
tWC Address tAW CS1 tAS CS2 tWP WE tWHZ Dout Din tDW tOW tDH tWR
Note : 1. During read cycle time, WE is to be "H" level. 2. During write cycle time that is controlled by CS1 or CS2, Output Buffer is in high impedance state, whether OE level is "H" or "L". 3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level. 4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals.
q DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
(VSS = 0V, Ta = -25 to 85C) Parameter Data retention Supply voltage Data retention current Chip select data hold time Operation recovery time
TTa
Symbol VDDR IDDR tCDR tR
Conditions
Min. 2.0
Typ. -- 0.5T 0.25T -- --
Max. 3.6 50
Unit V A
VDD = 2.7V CS1 = CS2VDD--0.2V or CS20.2V
LL SL
-- -- 0 5
25 -- -- ns ms
= 25C
Data retention timing
VDD tCDR CS1 2.7V
(CS1 Control)
2.7V tR CS1VDD--0.2V
Data retention timing
VDD tCDR 2.7V
(CS2 Control)
2.7V tR
Data hold mode VDDR2.0V
Data hold mode VDDR2.0V
VIH
VIH
CS2
VIL
CS20.2V
VIL
T when retaining data in standby mode, supply voltage can be lowered with in a certain range. But read or write cycle cannot be performed while the supply voltage is low.
4
SRM20V100LLMX7
s FUNCTIONS q Truth Table
CS1 H X L L L
X : "H" or "L"
CS2 X L H H H
OE X X X L H
WE X X L H H
DATA I/O Hi-Z Hi-Z Input data Output data Hi-Z
Mode Unselected Unselected Write Read Output disable
IDD IDDS, IDDS1 IDDS, IDDS1 IDDO IDDO IDDO
q Reading data
Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H". Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any other objective, then access time apparently is able to be cut down.
q Writing data
There are the following four ways of writing data into the memory. (1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1. (2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2. (3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE. (4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2. Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX7 at the end of the period that CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided.
q Standby mode
When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX7 is in the standby mode which has retaining data operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or "L". When CS1 and CS2 level are in the range over VDD-0.2V, CS2 level is in the range under 0.2V, in the SRM20V100LLMX7 there is almost no current flow except through the high resistance parts of the memory.
5
s PACKAGE DIMENSIONS
Plastic SOP6-32pin
32
(0.82max) (0.805 -0.003 )
17 20.450.1 +0.004
20.85max
(0.445 -0.004 )
(0.556 -0.011 )
11.2950.1 +0.003
14.1350.3 +0.012
0 8
(0.106 -0.003 )
1
16
2.70.1 +0.004
(0.122max)
3.1max
(0.006 -0.002 ) (0.05) (0.016 )
0.2 1.27 0.40.1 +0.003 -0.004
0.150.05 +0.001 0.80.2 +0.008
(0.008)
(0.031 -0.007 ) (0.056)
1.42
Unit : mm (inch)
Plastic TSOP ( I ) -32pin
(0.787 -0.007 ) (0.724 -0.007 )
0.2 18.4+0.008
Plastic TSOP ( I ) -32pin-R1
(0.787 -0.007 )
0.2 18.4+0.008 (0.724-0.007)
200.2 +0.008
200.2 +0.008
1
INDEX
32
16
17
(0.3150.007)
INDEX
16
17 0 10
1
32 0 10
(0.3150.007)
80.2
80.2
(0.05max)
(0.006 -0.003 )
0.1 0.5+0.003
-0.075 0.15 +0.002
+0.07
(0.039)
1
(0.006 -0.003 )
0.1 0.5+0.003
0.15 -0.075 +0.002
+0.07
(0.02 -0.004 ) (0.031 -0.007 )
0.80.2 +0.008
(0.02)
0.5
(0.008 -0.004 )
0.20.1 +0.003
(0.02 -0.004 ) (0.031-0.007)
0.80.2 +0.008
(0.02)
0.5
0.20.1 +0.003 (0.008 -0.004 )
Unit : mm (inch)
Unit : mm (inch)
Plastic Slim-TSOP ( I ) -32pin
(0.5280.011) (0.4650.003)
11.80.1 13.40.3
Plastic Slim-TSOP ( I ) -32pin-R1
(0.5280.011) (0.4650.003)
11.80.1 13.40.3
1
INDEX
32
16
17
(0.3150.007)
INDEX
16
17 0 10
1
32 0 10
(0.05max)
(0.3150.007)
80.2
80.2
(0.006 -0.003 )
0.1 0.5+0.003
-0.075 0.15 +0.002
+0.07
(0.006 -0.003 )
0.1 0.5+0.003
-0.075 0.15 +0.002
+0.07
(0.02 -0.004 ) (0.031 -0.007 )
0.80.2 +0.008
(0.02)
0.5
(0.008 -0.004 )
0.20.1 +0.003
(0.02 -0.004 ) (0.031 -0.007 )
0.80.2 +0.008
(0.02)
0.5
(0.008 -0.004 )
0.20.1 +0.003
Unit : mm (inch)
Unit : mm (inch)
6
(0.05max)
1.27max
(0.039)
(0.039)
1.27max
1
1
(0.05max)
1.27max
(0.039)
1.27max
1
SRM20V100LLMX7
s CHARACTERISTICS CURVES
Normalized IDDA--Ta 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -40 -20 0 20 40 Ta (C) 60 80 0.5 WRITE READ 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 1/tRC, 1/tWC Normalized IDDS1--VDD 100 VDD = 3.0V Ta = 25C 2.4 2.2 10 2 1.8 1.6 1.4 1 1 1.2 1 0.8 0.1 0.6 0.4 0.2 0.01 -40 -20 0 20 40 Ta (C) 60 80 0.1 2.4 2.7 3 3.3 VDD (V) 3.6 3.9 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 Ta = 25C VDD = 3.0V WRITE READ 1.1 1 0.9 0.8 0.7 0.6 2.4 2.7 3 3.3 VDD (V) 3.6 3.9 VDD = 3.0V READ, WRITE 1 0.9 0.8 0.7 0.6 Ta = 25C VDD = 3.0V Normalized IDDA--Frequency 1.6 1.5 1.4 1.3 1.2 WRITE READ Ta = 25C READ, WRITE Normalized IDDA--VDD
Normalized IDDS1--Ta 100
Normalized IOH--VOH
7
SRM20V100LLMX7
tACC Normalized tACS1--Ta tACS2 1.4 VDD = 3.0V 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -40 -20 0 20 40 Ta (C) 60 80 1.3 Ta = 25C 1.25 1.2 1.15 1.1 1.05 1 1 0.95 0.9 0.85 0.8 2.4 2.7 3 3.3 VDD (V) 3.6 3.9 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 VOL (V) 0.8 1 tACC Normalized tACS1--VDD tACS2 2.2 2 1.8 1.6 1.4 1.2 Ta = 25C VDD = 3.0V Normalized IOL--VOL
tACC Normalized tACS1--CL tACS2 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 100 100 Ta = 25C VDD = 3.0V 10
Normalized IDDR--Ta
VDD=2.7V
1
0.1
0.01 200 300 CL (pF) 400 -40 -20 0 20 40 60 Ta (C) 80
NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 1996 All right reserved.
ELECTRONIC DEVICE MARKETING DEPARTMENT
IC Marketing & Engineering Group 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5816 FAX: 0425-87-5624 International Marketing Department I (Europe & U. S. A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5812 FAX: 0425-87-5564
8 421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425-87-5814
International Marketing Department II (Asia) FAX: 0425-87-5110 First issue Oct. 1995, printed Feb. 1997 in Japan T

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